1. Field of the Invention
Embodiments of the present invention relate generally to a NAND flash memory device. More particularly, embodiments of the invention relate to a NAND flash memory device including a page buffer adapted to discharge a bit line voltage that increased due to coupling capacitance during an erase operation.
A claim of priority is made to Korean Patent Application No. 2005-47869, filed Jun. 3, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Discussion of Related Art
A NAND flash memory device typically comprises a memory cell array divided into several memory blocks. Each of the memory blocks generally comprises several cell strings, where each of the cell strings comprises a string selection transistor, a ground selection transistor, and plurality of memory cells serially connected between the string selection transistor and the ground selection transistor. Each of the memory cells comprises a transistor having a source, a drain, a bulk, a floating gate, and a control gate. The NAND flash memory device can perform write and program operations on individual cell strings. However, the NAND flash memory device can only perform an erase operation a memory block unit at a time.
In a NAND flash memory device, a program operation stores a logical ‘0’ in a memory cell by applying a program voltage Vpgm to memory cell's control gate, and causing current to flow between the memory cell's source and drain. Program voltage Vpgm causes electrons in the current to be stored in the memory cell's floating gate, thus increasing a threshold voltage Vth of the memory cell. Increasing threshold voltage Vth of the memory cell causes the memory cell to store a logical ‘0’. Where the memory cell stores logical ‘0’, it is called a “Programmed Cell”.
The NAND flash memory device performs an erase operation to store logical ‘1’ in a block of memory cells. The erase operation is performed by applying an erase voltage “Verase” to the bulk of the memory cells to remove electrons from the memory cells' floating gates. Removing electrons from the memory cells' floating gates reduces their respective threshold voltages. After an erase operation is performed on a block of memory cells, the cells are called “Erased Cell”, and each memory cell in the memory block stores a logical ‘1’. In general, erase voltage Verase is higher than an operating voltage Vcc of the NAND flash memory device. For instance, the erase voltage could be 20V while operating voltage Vcc was only 5V.
FIG. 1 is a cross-sectional view of a cell string in a conventional NAND flash memory. Referring to FIG. 1, a pocket p-type well (Pp-well) is formed with a predetermined depth in a p-type substrate surrounded by an n-type well (N-well). N+ regions doped with N+ impurities are isolated in the pocket p-type well, with channel regions interposed between the N+ regions.
During an erase operation, erase voltage Verase is applied to the pocket p-type well. Where erase voltage Verase is applied to the pocket p-type well, it is also applied to a bit line BL by a P-N junction forward bias. Since erase voltage Verase is generally higher than operating voltage Vcc, transistors connected to bit lines that receive erase voltage Verase must be capable of withstanding a voltage higher than operating voltage Vcc without breaking down. A transistor that does not break down under erase voltage Verase is considered to have “endurance” to erase voltage Verase. Such a transistor is also sometimes called a “High Voltage Transistor”.
Erase voltage Verase should not be directly applied to circuits, such as page buffers, that use power voltage Vcc, because doing so may cause transistors in the page buffers to experience breakdown. To prevent transistors in page buffers from receiving erase voltage Verase, NAND flash memory devices commonly include high voltage transistors between a cell array and a page buffer to disconnect the page buffers from erase voltage Verase.
Unfortunately, as the degree of integration in NAND flash memory devices increases, erase voltage Verase can still cause problems in the page buffers due to coupling capacitance between adjacent bit lines. For example, where erase voltage Verase is applied to a first bit line but not a second bit line adjacent to the first bit line, the voltage level of the second bit line may still be elevated due to coupling capacitance between the first and second bit lines. Under these conditions, a first high voltage transistor connected to the first bit line will typically turn off to disconnect the first bit line from a corresponding first page buffer. However, the elevated voltage level of the second bit line can still damage a corresponding second page buffer.